1. Field of the Invention
Embodiments of the invention relates to a liquid crystal display capable of reducing the number of output channels of a data driving circuit.
2. Discussion of the Related Art
An active matrix type liquid crystal display displays a moving picture using a thin film transistor (TFT) as a switching element. The active matrix type liquid crystal display has been implemented in televisions as well as display devices in portable devices such as office equipments and computers, because of the thin profile of the active matrix type liquid crystal displays. Accordingly, a cathode ray tube (CRT) is being rapidly replaced by the active matrix type liquid crystal display. Liquid crystal cells of the liquid crystal display displays an image by changing a transmittance depending on a voltage difference between a data voltage supplied to a pixel electrode and a common voltage supplied to a common electrode.
Measures for changing the connection configuration of liquid crystal cells of a liquid crystal display panel of the liquid crystal display are being continuously implemented, so as to reduce the number of output channels of a data driving circuit. FIG. 1 illustrates the comparison between a general normal panel and a double rate driving (DRD) panel for reducing the number of output channels.
The normal panel shown in (A) of FIG. 1 may realize a horizontal resolution of 800 using 2400 (=800×3(RGB)) data lines DL. Because output channels of the data driving circuit are respectively connected to the data lines DL, the data driving circuit for driving the normal panel requires 2400 output channels.
The DRD panel shown in (B) of FIG. 1 may realize a horizontal resolution of 800 using only 1200 data lines DL because a pair of adjacent left and right liquid crystal cells commonly use one data line DL positioned between the pair of left and right liquid crystal cells. Thus, the number of output channels of the data driving circuit for driving the DRD panel is reduced to one half (i.e., 1,200) of the number of output channels of the normal panel shown in (A) of FIG. 1.
However, the DRD panel has a panel rendering structure in which the liquid crystal cells sharing the data line DL receive data in a time-division manner. Thus, a timing controller has to change an alignment sequence of video data in accordance with the panel rendering structure. This is described in detail with reference to FIG. 2.
In general, an input sequence of video data input to the timing controller from a system board is in agreement with the normal panel rendering structure shown in (A) of FIG. 1. In this instance, the timing controller synchronizes the output sequence of the video data with the input sequence thereof from the system board as shown in (A) of FIG. 2. Namely, the timing controller outputs video data for one horizontal line to the data driving circuit in the order of R0, G0, B0, R1, G1, B1 . . . R799, G799, and B799.
On the other hand, in the DRD panel rendering structure shown in (B) of FIG. 1, video data is written in the direction indicated by the arrow shown in (B) of FIG. 1. Thus, the timing controller has to align video data input from the system board in the order of R0, G0, B0, R1, G1, B1 . . . R799, G799, and B799 in accordance with the data writing sequence indicated by the arrow direction. The timing controller time-divides one horizontal period for applying video data for 1 horizontal line, and respectively aligns pre-charge data for 1/2 horizontal line to be written first in the order  and post-charge data for 1/2 horizontal line to be written later in the order . The timing controller aligns the pre-charge data in the order of R0, R1, B1, R2, R3, B3 . . . R796, R797, B797, R798, R799, and B799, and then outputs the pre-charge data to the data driving circuit in this alignment sequence during the first half of the horizontal period. The pre-charge data includes all the red (R) data R0, R1, R2, R3 . . . R796, R797, R798, and R799, and one half odd-numbered blue (B) data B1, B3, B797, and B799, both of which are to be written within the one horizontal period. The timing controller aligns the post-charge data in the order of G0, B0, G1, G2, B2, G3 . . . G796, B796, G797, G798, B798, and G799, and then outputs the post-charge data to the data driving circuit in this alignment sequence during the second half of the horizontal period. The post-charge data includes all the green (G) data G0, G1, G2, G3 . . . G796, G797, G798, and G799 and the other half even-numbered blue (B) data B0, B2 . . . B796, and B798, both of which are to be written within the horizontal period.
As such, the liquid crystal display having the DRD panel necessarily requires a line memory for storing input video data for each horizontal line as shown in FIG. 3 because the alignment sequence of video data has to be changed in accordance with the panel rendering structure. This causes an increase in the manufacturing cost.